The 90 etch angle cell exhibited a slightly better oncurrent value of 6. Etch and deposition process challenges and solutions for 3d nand. On the other hand, pecvd is not easy in the concaveconvex structure or the deep hole pattern reaching the same thickness of the film, it ald process is expected to become more than 64. Deposition and etch processes define 3d nand memory array. Distortionfree profiles of channel and contact holes. Financial outperformance metrics shown for cy 2016 relative to cy 2014 baseline and are presented on a nongaap basis. Disclosed herein are 3d nand memory devices having an oxide semiconductor vertical nand channel and methods for forming 3d nand memory devices having an oxide semiconductor. Entegris solutions for the unique challenges of 3d nand design and manufacturing threedimensional verticallystacked memory architectures o. Innovation to advance moores law requires core technology revolution uc berkeley seminar march 9th, 2012. But i figured id describe it anyway, since its also a unique and critical and difficult. In this paper, 3d nand flash memory device and array architecture having the laterallyrecessed bitline stack are proposed. Unlike current nand flash memory chips that are built with a 2d planar structure. Vertical etch of the channel holes to later place the charge trap stack and the memory.
Fabricating 3d nand memory having monolithic crystalline. Technology and cost trends at advanced nodes scotten w. Covering new and old developments in atomic layer deposition. As impossible as that sounds, atomic layer deposition ald is a reality. Simple laterallyrecessed channel lrc cell structure is designed and fabricated. To address the lithography challenges at the 1x nodes and the wellknown scaling issues associated with planar nand, 3d flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to deposition and etch. The excess floatinggate polysilicon is then etched away e, leaving isolated floating gates in the recesses created in step b. The threedimensional structures in 3d nand memory devices require a high degree of process variability control. Us patent for method for manufacturing 3d nand memory. Imec advances drive current in vertical 3d nand memory. Concept of the ion enhanced chemical etching iece model x is the average number of b atoms in the abx molecule.
Samsung 3d v nand tem cross section showing the use of a ald al2o3 gate dielectric with a tinw metal gate stack connecting to the vertical charge trapping ono stack siosinsio with a central poly silicon substrate plate connection pillar. More than a trillion holes must be etched simultaneously and uniformly on every wafer, each with an aspect ratio of more than 40. Lateral etch uniformity enables 3d nand selectratm etch creates consistent contact resistance pre etch traditional etch selectra. In this paper we will present etch hardware and process development solutions provided to overcome these difficult etch challenges for staircase etch, hard mask open, gate trench etch, channel hole etch. Micron intel and sk hynix swiftly followed, and ymtc china is the newcomer.
However, the conduction in polysi channel is hampered by grain size and by scattering events at grain boundaries and charged defects. We present results of experimental measurements, simulations, and models to better understand etching of sin with h3po4 in 3d nand structures. Selected applications in logic, 3dnand, dram and emerging memory. Entegris solutions for 3d nand keywords materials performance, intelligen twostage pump, impact filter, linerbased photoresist dispense, ebm foup with diffuser purge, formulated chemistries for selective si3n4 removal, cfree ald precursors, contaminationfree solid precursor delivery, specialized filters, specilized purifiers.
Deposition systems, gas chemical etch systems, test systems. Overcoming challenges in 3d nand volume manufacturing lam. One parameter of note in 3d nand memory devices is the on current of the memory cell on the nand string, which is referred to as i cell. Ald metal oxides for etch stops, liners and pattern assist. Disclosed herein are 3d nand memory devices having an oxide semiconductor vertical nand channel and methods for forming the same.
Thus, conventional shrink technology, which is primarily based on dimension scaling, can not solely provide complete. Overcoming challenges in 3d nand volume manufacturing. Unlike scaling practices in 2d nand technology, the direct way to reduce bit costs and increase chip density in 3d nand is by adding layers. Har channel etch is the most critical and challenging step in 3d nand because it is key to achieving uniform hole size through multiple layers to define the channel of memory cells.
How do these developments affect the performance and reliability of storage systems. Finally, the tunnel oxide is deposited as the outer cylindrical layer, with the channel filling in at the end f. Samsung 3d vnand tem cross section showing the use of a ald al2o3 gate dielectric with a tinw metal gate stack connecting to the vertical charge trapping ono stack siosinsio with a. In fact, its being used in an everincreasing number. The icefill process completely fills the lateral horizontal lines without any voids, while at the same time minimizing deposition in the vertical channel area.
Impact of etch angles on cell characteristics in 3d nand. These are the major players in the manufacturing of 3d nand devices. Cy 2016 was calculated using actual performance year to. Deep hole etching simulation for advanced nand flash memory. However, the conduction in polysi channel is hampered by grain size. Etch and film ying zhang, shahid rauf, ajay ahatnagar, david chu, amulya athayde, and terry y. For deposition, etch, and clean steps, measurement of the mass change of a wafer before and after a process is a simple and direct means of monitoring and controlling process results, particularly for. Us9634097b2 3d nand with oxide semiconductor channel. Deep hole etching simulation for advanced nand flash. For dram technology, a doublegate array having vertical channel structure dgvc with 4f2 cell size is proposed, which can be fabricated on a bulk silicon wafer using the conventional memory process. Continue to focus on 3d nand and logic word line isolation slit multilevel contact dram 3d nand harc processes lower customer patterning costs through combining multiple steps into one improve our position in 9x12x through our clear lead in productivity and etch profile cy17 cy18 cy19 6x 6x9x 9x. As channels are then analyzed and benchmarked against the sireference, showing superior conduction properties for in concentration, x, higher than 0. The channel hole etch represents one of the most challenging processes due to both the high aspect ratio. This video shows film stack deposition, channel hole etch, stair etch, slit etch, and.
The xxxxx of the xxxxx dictates the need for ald deposition at the key steps. Talking in laymans terms, the 3d nand is just a stacking of memory chips on top of each other, where some manufacturers call this v vertical nand. Samsung is using an ald al2o3 gate dielectric for 3d vnand. Unlike planar nand, where scaling is primarily driven by lithography, 3d nand scaling is enabled by advances in deposition and etch processes. Enter the 3d era by kristian vatto nand scaling in vertical dimension does not have the same limitations as scaling in the x and y axes do. The industrys transition to 3d nand is being driven by several important advantages, including its ability to deliver higher capacity with a lower cost per. Ald is well suited for this and is used to form dielectric films on the sidewalls of memory holes. Continue to focus on 3d nand and logic word line isolation slit multilevel contact dram 3d nand harc processes lower customer patterning costs through. Simple laterallyrecessed channel lrc cell structure is designed and fabricated using a chemical dry etching cde system.
Ebeam, laser, uv, xray euv double patterning for logic quad patterning for memory laserbased processing. Introduction the nand flash memory cell has been refined to reduce the bit cost, but the limit of its miniaturization has been. The next generation of 3d nand devices demands specially formulated cleans customdesigned to work with a speci. Disclosed herein are methods for forming 3d nand memory devices having a monolithic crystalline or monocrystalline silicon vertical nand string channel. Separation of select gate planes by cut etch and removal of the memory cut etch. Deep hole etching simulation for advanced nand flash memory figure 1. Apr 25, 2017 disclosed herein are 3d nand memory devices having an oxide semiconductor vertical nand channel and methods for forming 3d nand memory devices having an oxide semiconductor vertical nand channel.
Etching of silicon nitride in 3d nand structures request pdf. An important part of 3d nand is how you access the word lines. Us9287290b1 3d memory having crystalline silicon nand. Variability control challenges for 3d nand stack channel. Perspectives of memory challenges from equipment supplier. Imagine being able to deposit a film of material just a few atomic layers at a time. Stack cells in a 3d structure to break through the technology bottleneck, samsung broke new grounds in three key. Samsung is using an ald al2o3 gate dielectric for 3d vnand samsung seems to be using an ald al2o3 gate dielectric with a tinw metal gate according to dick james at chipworks who recently reported on the matter in front of. The nand string channel may be a single crystal of silicon or have a few large grains of polysilicon. The results achieved in this research demonstrate that in x ga 1x as is very promising as channel material for future generation 3d nand memories. Materials properties and channel length must be uniform over fin height. Thus, conventional shrink technology, which is primarily based on dimension scaling, can not solely provide complete answers for sub50nm dram and nand flash manufacturing.
Using a proprietary filling technique, the new system creates the tungsten wordlines with an insideout atomic layer deposition ald process. Verticalchannel stacked array vcstar for 3d nand flash. In one embodiment, the oxide semiconductor vertical nand channel is a metal oxide semiconductor. In 20, samsung shipped the first v nand product using 24 layers and mlc 1. Alternative channel materials for 3d nand memories core. Technology for sub50nm dram and nand flash manufacturing. Dry etch 3d nand schematics courtesy of ic knowledge llc. Development of wetetch chemistries for tungsten wordline. Depending on the process, 10 different contacthole depths can usually be etched in one etch process, and thus four masks and four etch processes. Implementation of floating gate cells into 3d nand flash arrays. Entegris solutions for the unique challenges of 3d nand. In order for successful manufacturing, shrink technology must be.
In case of etching with oxygen, atomic scale etch rates were achieved with cyclic etch rates of 2. Silicon nitride etch wet etching techniques from blanket nitrideoxide wafers do not. Therefore, wet etch method is proposed as an alternative for w recess. Ald under these extreme har conditions and produce uniform films at. Key process steps in 3d nand etch and deposition processes. However, 3d nand needs to consume enormous time for garbage. Perspectives of memory challenges from equipment supplier jeffrey marks. Mediumterm management plan gray progress and tel initiatives. Early applications of 3d nand technology began in 2007, led by both toshiba bit cost scalable, bics and samsung vertical nand or v nand.
Imec advances drive current in vertical 3d nand memory devices 8 december 2015, by hanne degans typical idvg. Lams new products deliver critical capability for building. Equipment and process technologies for 3d structural devices. Imec advances drive current in vertical 3d nand memory devices.
Select gate channel formation by hole etch stopping on memory string channel poly 44 figure 45. According to harmeet singh at lam research, issues include incomplete etching. Stack cells in a 3d structure to break through the technology bottleneck, samsung broke new grounds in three key areas. Disclosed herein are 3d nand memory devices having vertical nand strings with a crystalline silicon channel and techniques for fabricating the same.
For deposition, etch, and clean steps, measurement of the mass change of a wafer before and after a process is a simple and direct means of monitoring and controlling process results, particularly for ultrathin films, ultrathick films, and complex 3d geometries of newer chip designs, where traditional optical metrology techniques are ineffective. Request pdf verticalchannel stacked array vcstar for 3d nand flash memory recently, 3d stacked nand flash architectures have been proposed to solve scaling limit of the planar nand flash. Jun 23, 2016 disclosed herein are methods for forming 3d nand memory devices having a monolithic crystalline or monocrystalline silicon vertical nand string channel. Five years later, in 2018, vendors of 3d nand have all announced production plans for 96layer nand using tlc 2. Ald process is expected to become more than 64 layers of. Nov 18, 2016 3d nand is a technology inflection that enables higher density memories.
In 20, samsung shipped the first vnand product using 24. Current 2d nand scaling is approaching technology limitation in both lithography and device performance arena. More than a trillion holes need to be etched on every wafer. Image sensor, mram, rram global innovation extreme customer concentration fabless vertical fabless system houses 300mm 450mm logic finfet nand 3d nand dram 6f2 3d 4f2 new energy sources. The channel of the verticallyoriented nand string may be cylindrically shaped. The nand string channel may be a single crystal of. Fabrication process flow of the stacked lrc cells is explained in detail. Fabrication flows of dram, 3d nand and logic device. Every time they shrink, litho is a problem requiring more multipatterning litho i.